cys tech electronics corp. s pec. no. : c355 c3 issued date : 20 10.07.23 revised date : 2 0 1 1 .1 1.03 page no. : 1/6 dtc1 1 4 y c3 c y s t ek product s pecification npn digital transistors (built-in resistors ) DTC114YC3 features ? built-in bias resistors enable the configuration of an inverter circu it without connecting external input resistors (see equi valent circuit). ? the bias resistors consist of thin -film resistors with complete isolat ion to allow negative biasing of the input. they also have the advantage of almost completely eliminating parasitic effects. ? only the on/off conditions need to be set for operation, making device design easy. ? complements the dta114yc3 equivalent circuit outline sot-523 DTC114YC3 r1=10k , r2=47 k in(b) : base out(c) : collector gnd(e) : emitter absolute maximum ratings (ta=25 c) parameter symbol limits unit supply v o ltage v cc 50 v input voltage v i -6~+40 v i o 70 ma output current i o(max.) 100 ma power dissipation pd 150 mw thermal resistance, junction to ambient r ja 833 c/w junction temperature tj 150 c storage temperature tstg -55~+150 c http://
cys tech electronics corp. s pec. no. : c355 c3 issued date : 20 10.07.23 revised date : 2 0 1 1 .1 1.03 page no. : 2/6 dtc1 1 4 y c3 c y s t ek product s pecification electrical characteristics (ta=25 c) parameter symbol min. typ. max. unit test conditions vi(off) - - 0.3 v vcc=5v, io=100ua input voltage vi(on) 3 - - v vo=0.3v, io=1ma output voltage vo(on) - 0.1 0.3 v io/ii=5ma/0.25ma input current ii - - 0.88 ma vi=5v output current io(off) - - 0.5 ua vcc=50v, vi=0v dc current gain gi 68 - - - vo=5v, io=5ma input resistance r1 7 10 13 k - resistance ratio r2/r1 3.7 4.7 5.7 - - transition frequency f t - 250 - mhz v ce =10v, i c =5ma, f=100mhz * * transition frequency of the device ordering information device package shipping marking DTC114YC3 sot-523 (pb-free package) 3000 pcs / tape & reel 64
cys tech electronics corp. s pec. no. : c355 c3 issued date : 20 10.07.23 revised date : 2 0 1 1 .1 1.03 page no. : 3/6 dtc1 1 4 y c3 c y s t ek product s pecification typical characteristics d c c urre n t g a i n vs o ut pu t curre nt 10 10 0 1 000 11 0 1 0 0 o ut p ut v ol t a ge vs o ut put c urre nt 10 100 1000 11 0 1 0 0 o u t p u t c urre n t --- io (ma ) o u t p u t v o l t a g e ---v o (o n )(mv ) o u t p u t c u r r e n t ---i o ( ma ) c u rre nt g a i n -- - hf e vo=5v io/ii=20 i np ut v o l t a g e vs o ut put c ur r e nt ( o n c ha r a c t e r i s t i c s ) 0.1 1 10 0. 1 1 10 1 00 o ut put c ur r e nt - - - i o ( m a ) in p u t v o l t a g e -- - v i ( o n )(v ) vo=0.3v o u tp u t c u r r e n t v s i n p u t v o l t ag e ( o f f c h a r acter i s t i cs ) 0.1 1 10 100 0. 1 1 1 0 inp u t v o l t a g e --- v i ( o f f)(v ) o u t p u t c u rre n t --- io (ma ) vcc=5v p o w e r d e ra t i ng curve 0 20 40 60 80 100 120 140 160 0 50 1 00 150 200 a m b i e n t t e mp e r a t u r e --- t a ( ) p o w e r d i s s i p a t i o n ---p d ( mw )
cys tech electronics corp. s pec. no. : c355 c3 issued date : 20 10.07.23 revised date : 2 0 1 1 .1 1.03 page no. : 4/6 dtc1 1 4 y c3 c y s t ek product s pecification reel dimension carrier tape dimension
cys tech electronics corp. s pec. no. : c355 c3 issued date : 20 10.07.23 revised date : 2 0 1 1 .1 1.03 page no. : 5/6 dtc1 1 4 y c3 c y s t ek product s pecification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cys tech electronics corp. s pec. no. : c355 c3 issued date : 20 10.07.23 revised date : 2 0 1 1 .1 1.03 page no. : 6/6 dtc1 1 4 y c3 c y s t ek product s pecification sot -523 dimension *: typical inches s t yle: pin 1.base (input) 2.emitter (grou nd) 3.collector (output) 3-l ead sot - 523 pla s tic surface mou n ted packa g e cys t ek pa ckage code: c3 marking: 64 millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.028 0.035 0.700 0.900 e 0.028 0.035 0.700 0.900 a1 0.000 0.004 0.000 0.100 e1 0.057 0.069 1.450 1.750 a2 0.028 0.031 0.700 0.800 e 0.020* 0.500* b1 0.006 0.010 0.150 0.250 e1 0.035 0.043 0.900 1.100 b2 0.010 0.014 0.250 0.350 l 0.016 ref 0.400 ref c 0.004 0.008 0.100 0.200 l1 0.010 0.018 0.260 0.460 d 0.059 0.067 1.500 1.700 0 8 0 8 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0 important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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